Alex Forencich
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c0583aaff5
|
eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:37:12 -08:00 |
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Alex Forencich
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1dc5463f00
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eth: Add GMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:34:49 -08:00 |
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Alex Forencich
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175230eeaf
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eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 20:46:31 -08:00 |
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Alex Forencich
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af912cc849
|
eth: Add MII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 20:05:41 -08:00 |
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Alex Forencich
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da7fe065cc
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io: Rework generic ODDR implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 19:27:56 -08:00 |
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Alex Forencich
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5c8037093b
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eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 18:06:41 -08:00 |
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Alex Forencich
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e3d8ad8d36
|
io: Add source-synchronous IO modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 15:44:34 -08:00 |
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Alex Forencich
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e18a2b3457
|
io: Add generic IDDR and ODDR modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 15:41:56 -08:00 |
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Alex Forencich
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fc1e0efad7
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ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:07:46 -08:00 |
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Alex Forencich
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ad0d44616b
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ptp: Add PTP TD leaf clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 20:18:17 -08:00 |
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Alex Forencich
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68c547b219
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ptp: Minor cleanup in PTP CDC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 20:17:21 -08:00 |
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Alex Forencich
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2eaa2f64a2
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ptp: Add PTP TD PHC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:50:16 -08:00 |
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Alex Forencich
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38a150b87a
|
ptp: Add PTP period output module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:06:46 -08:00 |
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Alex Forencich
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2abe774f8a
|
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:48:54 -08:00 |
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Alex Forencich
|
90650aee69
|
eth: Add 10G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:47:54 -08:00 |
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Alex Forencich
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d76e810033
|
axis: Fix parameter sizing in AXI stream FIFOs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-13 13:46:56 -08:00 |
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Alex Forencich
|
f356fad6fe
|
ptp: Add PTP clock CDC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 12:49:42 -08:00 |
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Alex Forencich
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17b4c37a1e
|
ptp: Add PTP clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 10:52:27 -08:00 |
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Alex Forencich
|
04b73e7ddf
|
eth: Add 1G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:12:57 -08:00 |
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Alex Forencich
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8f8572bdee
|
eth: Add taxi_axis_if to MAC file list files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 15:54:15 -08:00 |
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Alex Forencich
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2616e3f3e3
|
eth: Add 10G Ethernet combined MAC+PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:40:50 -08:00 |
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Alex Forencich
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0ddb89b18f
|
eth: Add 10G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:26:03 -08:00 |
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Alex Forencich
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fa73f9c1d5
|
eth: Add 1G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:25:48 -08:00 |
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Alex Forencich
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8d3d703656
|
eth: Add MAC control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 19:59:11 -08:00 |
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Alex Forencich
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96e348ac84
|
eth: Invert TX completion output control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 23:24:28 -08:00 |
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Alex Forencich
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72dabc5a9a
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:23 -08:00 |
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Alex Forencich
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2af4e7af3e
|
eth: Add AXI stream 64-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:15 -08:00 |
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Alex Forencich
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a375eb342d
|
eth: Add AXI stream 32-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:06 -08:00 |
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Alex Forencich
|
c914adf9f1
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:02:48 -08:00 |
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Alex Forencich
|
e3f047d735
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:27:27 -08:00 |
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Alex Forencich
|
f0f2a25943
|
eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:54 -08:00 |
|
Alex Forencich
|
8046a46680
|
eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:06 -08:00 |
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Alex Forencich
|
3f501aaac9
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:12:58 -08:00 |
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Alex Forencich
|
d52aa2f97e
|
axis: Add AXI stream combination async FIFO/adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-06 00:52:04 -08:00 |
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Alex Forencich
|
69e5ae8545
|
axis: Add AXI stream async FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-06 00:46:39 -08:00 |
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Alex Forencich
|
584f2a6542
|
eth: Add MAC pause control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 21:11:14 -08:00 |
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Alex Forencich
|
f479a85155
|
lfsr: Add LFSR descrambler module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:29:12 -08:00 |
|
Alex Forencich
|
e6ea90be36
|
lfsr: Add LFSR scrambler module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:28:57 -08:00 |
|
Alex Forencich
|
aeedc3bf7d
|
lfsr: Add LFSR PRBS checker module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:28:31 -08:00 |
|
Alex Forencich
|
328a00e30f
|
lfsr: Add LFSR PRBS generator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:28:08 -08:00 |
|
Alex Forencich
|
fb69371974
|
lfsr: Add LFSR CRC computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:27:44 -08:00 |
|
Alex Forencich
|
e35d2b2c03
|
eth: Add 10G PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 17:10:21 -08:00 |
|
Alex Forencich
|
c6ea4071eb
|
eth: Add XGMII/BASE-R encode/decode modules and testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 16:14:32 -08:00 |
|
Alex Forencich
|
8ee1f5cd18
|
lfsr: Add parametrizable LFSR module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 15:39:33 -08:00 |
|
Alex Forencich
|
f0c9f69987
|
axis: Add COBS encoder module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 11:49:50 -08:00 |
|
Alex Forencich
|
215732b309
|
axis: Work around verilator linter bug in AXI stream FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 11:40:14 -08:00 |
|
Alex Forencich
|
9138a7a51e
|
axis: Add COBS decoder module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 11:39:38 -08:00 |
|
Alex Forencich
|
85eb59f747
|
axis: Add AXI stream broadcaster module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 10:38:15 -08:00 |
|
Alex Forencich
|
beb36b78e0
|
io: Add switch debounce module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-04 00:16:34 -08:00 |
|
Alex Forencich
|
6ba257aa10
|
sync: Add signal synchronizer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-03 23:43:18 -08:00 |
|