Alex Forencich
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b468d92e39
|
hip: Report error if fractional MMCM configuration does not work
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-17 21:00:12 -07:00 |
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Alex Forencich
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eacae099bf
|
hip: Add fractional MMCM wrapper for generating offset clocks for DDMTD
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-13 21:00:09 -07:00 |
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Alex Forencich
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ebeadee172
|
lss: Implement fractional baud rate generation for UART
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-11 23:49:39 -07:00 |
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Alex Forencich
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1c686391ab
|
lss: Refactor UART module to split out and share baud rate generation logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-11 23:09:19 -07:00 |
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Alex Forencich
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7df14e54e5
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xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-11 18:33:57 -07:00 |
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Alex Forencich
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15653923fd
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xfcp: Add XFCP switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-10 15:30:59 -07:00 |
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Alex Forencich
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0ee729b744
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xfcp: Add XFCP AXI module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:28:05 -07:00 |
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Alex Forencich
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70d77c8a95
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xfcp: Add XFCP AXI lite module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:25:55 -07:00 |
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Alex Forencich
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ed9e8ffab3
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eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 11:05:58 -08:00 |
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Alex Forencich
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024353c68a
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lss: Add MDIO master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 23:48:57 -08:00 |
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Alex Forencich
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ed325acb1e
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axis: Implement tstrb in pipeline FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:18:20 -08:00 |
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Alex Forencich
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e9ac4947ba
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axis: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:17:05 -08:00 |
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Alex Forencich
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56215865da
|
axi: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:16:29 -08:00 |
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Alex Forencich
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c422297666
|
axis: Tie off unused sideband signals in COBS encoder
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:11:38 -08:00 |
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Alex Forencich
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194a686bda
|
xfcp: Add XFCP UART interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-04 22:05:11 -08:00 |
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Alex Forencich
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98ea651532
|
axis: Use unpacked arrays for unpacking interface signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:56 -08:00 |
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Alex Forencich
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56a3c9f1ba
|
axis: Add AXI stream arbitrated multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:40 -08:00 |
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Alex Forencich
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46e60d32f2
|
prim: Add arbiter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:49 -08:00 |
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Alex Forencich
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5966d05740
|
prim: Add priority encoder and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:32 -08:00 |
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Alex Forencich
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a790e270b8
|
axi: Replace reg with logic in AXI lite RAM
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:44:18 -08:00 |
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Alex Forencich
|
df300b7dad
|
axis: Add AXI stream multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:28:02 -08:00 |
|
Alex Forencich
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ad3042e090
|
axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:58:30 -08:00 |
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Alex Forencich
|
55c097f47d
|
axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:27:11 -08:00 |
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Alex Forencich
|
0632b1982e
|
axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:26:03 -08:00 |
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Alex Forencich
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ae26b61200
|
axi: Add AXI register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:08:39 -08:00 |
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Alex Forencich
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1075896ecc
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axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:02:50 -08:00 |
|
Alex Forencich
|
5e5bce9aa0
|
axi: Add SV interface for AXI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:51:25 -08:00 |
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Alex Forencich
|
5f9f71e615
|
axi: Add SV interface for AXI lite
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:51:16 -08:00 |
|
Alex Forencich
|
f419b3167a
|
axis: Switch AXI stream interface license to MIT
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:50:40 -08:00 |
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Alex Forencich
|
c6cbb57fe7
|
lss: Extract UART data width setting from interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 14:15:42 -08:00 |
|
Alex Forencich
|
cf44abae0d
|
axis: Use signal sync module for async FIFO output pause
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:13:10 -08:00 |
|
Alex Forencich
|
181691941f
|
eth: Use signal sync module for RGMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:12:50 -08:00 |
|
Alex Forencich
|
f8d5d6a45e
|
eth: Use signal sync module for GMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:12:10 -08:00 |
|
Alex Forencich
|
64c1cb1e39
|
eth: Use signal sync module for internal MAC pause handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 16:27:37 -08:00 |
|
Alex Forencich
|
5a8ac23922
|
io: Add LED shift register driver module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 15:44:57 -08:00 |
|
Alex Forencich
|
916355ca8a
|
eth: Add TX/RX polarity control to MAC+PHY+GT wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-24 17:17:23 -08:00 |
|
Alex Forencich
|
7047cb5c4f
|
eth: Tie off transceiver control signals during simulation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-24 16:28:59 -08:00 |
|
Alex Forencich
|
f0ec82a384
|
eth: Add MAC+PHY+GT wrapper for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:22:54 -08:00 |
|
Alex Forencich
|
7613cae4f0
|
eth: Use 2D array for PFC config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:08:43 -08:00 |
|
Alex Forencich
|
7f2ecf9b49
|
eth: Implement RX sequence error reporting in MAC+PHY module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 10:16:32 -08:00 |
|
Alex Forencich
|
422c54229e
|
eth: Split block type checks in MAC+PHY to reduce fanin
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 10:02:08 -08:00 |
|
Alex Forencich
|
8f6a99112b
|
eth: Add missing block types to MAC+PHY logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 09:55:28 -08:00 |
|
Alex Forencich
|
6a294cef2c
|
Use string type for string parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-21 19:14:28 -08:00 |
|
Alex Forencich
|
6154506c0a
|
axis: Use reset synchronizer module in AXI stream async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-20 12:44:23 -08:00 |
|
Alex Forencich
|
17f3613ca4
|
eth: Clean up function definitions
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-20 12:21:33 -08:00 |
|
Alex Forencich
|
94dba88560
|
eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:42 -08:00 |
|
Alex Forencich
|
255b26d2f2
|
eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:22 -08:00 |
|
Alex Forencich
|
baa5f72a6c
|
eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:16:54 -08:00 |
|
Alex Forencich
|
ffaf05f2d1
|
eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:05:59 -08:00 |
|
Alex Forencich
|
fab49d1435
|
eth: Add RGMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:50:42 -08:00 |
|