Byron Lathi
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fd4dbfaf81
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Merge branch '38-increase-cpu-speed' into 'master'
Resolve "Increase CPU Speed"
Closes #38
See merge request bslathi19/super6502!33
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2023-10-16 01:45:44 +00:00 |
|
Byron Lathi
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e768b245bd
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rework state machine
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2023-10-15 18:24:19 -07:00 |
|
Byron Lathi
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362c9f140f
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Fix synthesis issue
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2023-10-15 13:52:55 -07:00 |
|
Byron Lathi
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e0e20d7fb4
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Add indirect test
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2023-10-15 13:41:51 -07:00 |
|
Byron Lathi
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32f6c0f8d9
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Add jsr test
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2023-10-15 13:30:09 -07:00 |
|
Byron Lathi
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afd8de92cc
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Fix sdram wrapper state machine
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2023-10-15 13:12:46 -07:00 |
|
Byron Lathi
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673386f9f9
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Change clk_2 to clk_cpu
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2023-10-12 19:32:12 -07:00 |
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Byron Lathi
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893a0f1a9e
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Merge branch '37-run-full-boot-simulation-as-part-of-ci' into 'master'
Resolve "Run full boot simulation as part of CI"
Closes #37
See merge request bslathi19/super6502!32
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2023-10-11 08:43:33 +00:00 |
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Byron Lathi
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448d9add89
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Use repo based path for creating fs image
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2023-10-11 01:06:50 -07:00 |
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Byron Lathi
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4988d458b7
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full sim requires toolchain
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2023-10-11 01:02:41 -07:00 |
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Byron Lathi
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d3ea5ed4d1
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Use udisksctl
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2023-10-11 00:59:41 -07:00 |
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Byron Lathi
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3900093349
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Merge branch '34-sd-card-spi-mode-testbench' into 'master'
Resolve "SD Card SPI mode testbench"
Closes #34
See merge request bslathi19/super6502!29
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2023-10-11 05:15:25 +00:00 |
|
Byron Lathi
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8e70e5a7c4
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Update verilog sd
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2023-10-10 21:40:24 -07:00 |
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Byron Lathi
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57efb41ae0
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Increase sim time, update verilog sd
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2023-10-10 21:39:10 -07:00 |
|
Byron Lathi
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97622ac3bb
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Update verilog sd
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2023-10-09 23:32:55 -07:00 |
|
Byron Lathi
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7bb2dd9a7f
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Update verilog sd
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2023-10-09 22:33:44 -07:00 |
|
Byron Lathi
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67fa368319
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Update verilog sd
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2023-10-09 21:13:21 -07:00 |
|
Byron Lathi
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fc13114e49
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Update verilog sd
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2023-10-09 21:07:36 -07:00 |
|
Byron Lathi
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532364b8d2
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remove sd from regular sim
Figure out how to do this later
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2023-10-06 22:08:40 -07:00 |
|
Byron Lathi
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fe72a4e9ea
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Remove dependency on file, since its created anyway
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2023-10-06 13:21:54 -07:00 |
|
Byron Lathi
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d27e442d5e
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Use REPO_TOP in script, call script from makefile
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2023-10-06 13:18:36 -07:00 |
|
Byron Lathi
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a5ff9fb5da
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Update verilog sd
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2023-10-06 12:46:29 -07:00 |
|
Byron Lathi
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a3e0ab0e1e
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Use 8 bit memory !! Will eat all your RAM!
Figure out a better way to load memories that doesn't immediately oom
you.
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2023-10-06 07:28:34 -07:00 |
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Byron Lathi
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2084054d3d
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Add script for creating verilog filesystem image
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2023-10-06 06:48:47 -07:00 |
|
Byron Lathi
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2b98ad1522
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Increase sim time to get into sd block reads
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2023-10-04 22:50:55 -07:00 |
|
Byron Lathi
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e6e3044f25
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update sd emulator
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2023-10-04 20:27:25 -07:00 |
|
Byron Lathi
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6a684f62f8
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Remove another wait, update sd emulator
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2023-10-04 20:24:56 -07:00 |
|
Byron Lathi
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019b9c8120
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Update sd, remove wait state
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2023-10-04 19:11:45 -07:00 |
|
Byron Lathi
|
c1f7b33dda
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Update sd card emu
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2023-10-03 23:08:56 -07:00 |
|
Byron Lathi
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3a211faed7
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Don't have sd wait in simulation
need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim
also bro the sim is like 8000x slower than irl.
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2023-09-30 17:40:01 -07:00 |
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Byron Lathi
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cc32430f2a
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Refactor makefile, update verilog-sd-emulator
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2023-09-29 23:48:28 -07:00 |
|
Byron Lathi
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29aa369b33
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Merge branch 'master' into 34-sd-card-spi-mode-testbench
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2023-09-29 22:18:06 -07:00 |
|
Byron Lathi
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6d49e752bf
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Merge branch '36-run-simulation-as-part-of-ci' into 'master'
Resolve "Run simulation as part of ci"
Closes #36
See merge request bslathi19/super6502!31
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2023-09-30 05:05:12 +00:00 |
|
Byron Lathi
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f8bdbfbb2b
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Resolve "Run simulation as part of ci"
|
2023-09-30 05:05:12 +00:00 |
|
Byron Lathi
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907e5e9227
|
Merge branch '33-use-dependencies-instead-of-makefile-chaining-2' into 'master'
Resolve "Use dependencies instead of makefile chaining"
Closes #33
See merge request bslathi19/super6502!30
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2023-09-30 04:16:52 +00:00 |
|
Byron Lathi
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d3d3fea916
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Resolve "Use dependencies instead of makefile chaining"
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2023-09-30 04:16:52 +00:00 |
|
Byron Lathi
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913351efd4
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Add sd emulator as submodule
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2023-09-28 23:09:47 -07:00 |
|
Byron Lathi
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74f69378e8
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Merge branch '32-add-build-check-to-ci' into 'master'
Resolve "Add build check to CI"
See merge request bslathi19/super6502!27
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2023-09-29 05:14:52 +00:00 |
|
Byron Lathi
|
62967aa88d
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Resolve "Add build check to CI"
|
2023-09-29 05:14:52 +00:00 |
|
Byron Lathi
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624d662669
|
Merge branch '32-add-build-check-to-ci' into 'master'
Resolve "Add build check to CI"
Closes #32
See merge request bslathi19/super6502!25
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2023-09-29 04:37:07 +00:00 |
|
Byron Lathi
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df89962932
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remove env call
|
2023-09-28 21:34:42 -07:00 |
|
Byron Lathi
|
d5bb93f9c9
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Fix the bad commit
|
2023-09-28 21:30:38 -07:00 |
|
Byron Lathi
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8d4e2a11b0
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Merge branch '32-add-build-check-to-ci' of https://git.byronlathi.com/bslathi19/super6502 into 32-add-build-check-to-ci
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2023-09-28 21:29:40 -07:00 |
|
Byron Lathi
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d113498459
|
Try a bad commit
|
2023-09-28 21:28:39 -07:00 |
|
Byron Lathi
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801732b5c8
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Merge branch 'add_ci' into '32-add-build-check-to-ci'
Update .gitlab-ci.yml file
See merge request bslathi19/super6502!26
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2023-09-29 04:25:54 +00:00 |
|
Byron Lathi
|
59f88ead3f
|
Update .gitlab-ci.yml file
|
2023-09-29 04:25:54 +00:00 |
|
Byron Lathi
|
1b838169d3
|
Merge branch '31-show-uart-messages-in-sim-log' into 'master'
Resolve "Show UART messages in sim log"
Closes #31
See merge request bslathi19/super6502!24
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2023-09-28 06:14:00 +00:00 |
|
Byron Lathi
|
85f53816f9
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Remove unneeded CR
|
2023-09-27 23:03:22 -07:00 |
|
Byron Lathi
|
4925354f53
|
Fix uart status multiple drivers
|
2023-09-27 23:02:53 -07:00 |
|
Byron Lathi
|
4d0abbb508
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Add sim uart
|
2023-09-27 22:15:27 -07:00 |
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