Byron Lathi
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d3ea5ed4d1
|
Use udisksctl
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2023-10-11 00:59:41 -07:00 |
|
Byron Lathi
|
3900093349
|
Merge branch '34-sd-card-spi-mode-testbench' into 'master'
Resolve "SD Card SPI mode testbench"
Closes #34
See merge request bslathi19/super6502!29
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2023-10-11 05:15:25 +00:00 |
|
Byron Lathi
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8e70e5a7c4
|
Update verilog sd
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2023-10-10 21:40:24 -07:00 |
|
Byron Lathi
|
57efb41ae0
|
Increase sim time, update verilog sd
|
2023-10-10 21:39:10 -07:00 |
|
Byron Lathi
|
97622ac3bb
|
Update verilog sd
|
2023-10-09 23:32:55 -07:00 |
|
Byron Lathi
|
7bb2dd9a7f
|
Update verilog sd
|
2023-10-09 22:33:44 -07:00 |
|
Byron Lathi
|
67fa368319
|
Update verilog sd
|
2023-10-09 21:13:21 -07:00 |
|
Byron Lathi
|
fc13114e49
|
Update verilog sd
|
2023-10-09 21:07:36 -07:00 |
|
Byron Lathi
|
532364b8d2
|
remove sd from regular sim
Figure out how to do this later
|
2023-10-06 22:08:40 -07:00 |
|
Byron Lathi
|
fe72a4e9ea
|
Remove dependency on file, since its created anyway
|
2023-10-06 13:21:54 -07:00 |
|
Byron Lathi
|
d27e442d5e
|
Use REPO_TOP in script, call script from makefile
|
2023-10-06 13:18:36 -07:00 |
|
Byron Lathi
|
a5ff9fb5da
|
Update verilog sd
|
2023-10-06 12:46:29 -07:00 |
|
Byron Lathi
|
a3e0ab0e1e
|
Use 8 bit memory !! Will eat all your RAM!
Figure out a better way to load memories that doesn't immediately oom
you.
|
2023-10-06 07:28:34 -07:00 |
|
Byron Lathi
|
2084054d3d
|
Add script for creating verilog filesystem image
|
2023-10-06 06:48:47 -07:00 |
|
Byron Lathi
|
2b98ad1522
|
Increase sim time to get into sd block reads
|
2023-10-04 22:50:55 -07:00 |
|
Byron Lathi
|
e6e3044f25
|
update sd emulator
|
2023-10-04 20:27:25 -07:00 |
|
Byron Lathi
|
6a684f62f8
|
Remove another wait, update sd emulator
|
2023-10-04 20:24:56 -07:00 |
|
Byron Lathi
|
019b9c8120
|
Update sd, remove wait state
|
2023-10-04 19:11:45 -07:00 |
|
Byron Lathi
|
c1f7b33dda
|
Update sd card emu
|
2023-10-03 23:08:56 -07:00 |
|
Byron Lathi
|
3a211faed7
|
Don't have sd wait in simulation
need to figure out how to set that RTL_SIM flag only when we are
compiling code for the sim
also bro the sim is like 8000x slower than irl.
|
2023-09-30 17:40:01 -07:00 |
|
Byron Lathi
|
cc32430f2a
|
Refactor makefile, update verilog-sd-emulator
|
2023-09-29 23:48:28 -07:00 |
|
Byron Lathi
|
29aa369b33
|
Merge branch 'master' into 34-sd-card-spi-mode-testbench
|
2023-09-29 22:18:06 -07:00 |
|
Byron Lathi
|
6d49e752bf
|
Merge branch '36-run-simulation-as-part-of-ci' into 'master'
Resolve "Run simulation as part of ci"
Closes #36
See merge request bslathi19/super6502!31
|
2023-09-30 05:05:12 +00:00 |
|
Byron Lathi
|
f8bdbfbb2b
|
Resolve "Run simulation as part of ci"
|
2023-09-30 05:05:12 +00:00 |
|
Byron Lathi
|
907e5e9227
|
Merge branch '33-use-dependencies-instead-of-makefile-chaining-2' into 'master'
Resolve "Use dependencies instead of makefile chaining"
Closes #33
See merge request bslathi19/super6502!30
|
2023-09-30 04:16:52 +00:00 |
|
Byron Lathi
|
d3d3fea916
|
Resolve "Use dependencies instead of makefile chaining"
|
2023-09-30 04:16:52 +00:00 |
|
Byron Lathi
|
913351efd4
|
Add sd emulator as submodule
|
2023-09-28 23:09:47 -07:00 |
|
Byron Lathi
|
74f69378e8
|
Merge branch '32-add-build-check-to-ci' into 'master'
Resolve "Add build check to CI"
See merge request bslathi19/super6502!27
|
2023-09-29 05:14:52 +00:00 |
|
Byron Lathi
|
62967aa88d
|
Resolve "Add build check to CI"
|
2023-09-29 05:14:52 +00:00 |
|
Byron Lathi
|
624d662669
|
Merge branch '32-add-build-check-to-ci' into 'master'
Resolve "Add build check to CI"
Closes #32
See merge request bslathi19/super6502!25
|
2023-09-29 04:37:07 +00:00 |
|
Byron Lathi
|
df89962932
|
remove env call
|
2023-09-28 21:34:42 -07:00 |
|
Byron Lathi
|
d5bb93f9c9
|
Fix the bad commit
|
2023-09-28 21:30:38 -07:00 |
|
Byron Lathi
|
8d4e2a11b0
|
Merge branch '32-add-build-check-to-ci' of https://git.byronlathi.com/bslathi19/super6502 into 32-add-build-check-to-ci
|
2023-09-28 21:29:40 -07:00 |
|
Byron Lathi
|
d113498459
|
Try a bad commit
|
2023-09-28 21:28:39 -07:00 |
|
Byron Lathi
|
801732b5c8
|
Merge branch 'add_ci' into '32-add-build-check-to-ci'
Update .gitlab-ci.yml file
See merge request bslathi19/super6502!26
|
2023-09-29 04:25:54 +00:00 |
|
Byron Lathi
|
59f88ead3f
|
Update .gitlab-ci.yml file
|
2023-09-29 04:25:54 +00:00 |
|
Byron Lathi
|
1b838169d3
|
Merge branch '31-show-uart-messages-in-sim-log' into 'master'
Resolve "Show UART messages in sim log"
Closes #31
See merge request bslathi19/super6502!24
|
2023-09-28 06:14:00 +00:00 |
|
Byron Lathi
|
85f53816f9
|
Remove unneeded CR
|
2023-09-27 23:03:22 -07:00 |
|
Byron Lathi
|
4925354f53
|
Fix uart status multiple drivers
|
2023-09-27 23:02:53 -07:00 |
|
Byron Lathi
|
4d0abbb508
|
Add sim uart
|
2023-09-27 22:15:27 -07:00 |
|
Byron Lathi
|
a76763bdc7
|
Merge branch '23-create-a-better-simulation-environment' into 'master'
Resolve "Create a better simulation environment"
Closes #23
See merge request bslathi19/super6502!23
|
2023-09-28 04:16:59 +00:00 |
|
Byron Lathi
|
9e19a1eb72
|
Disable sdr debug, initialize uart status
|
2023-09-27 21:14:09 -07:00 |
|
Byron Lathi
|
ec4c3bab86
|
Update verilog-6502 bslathi19/verilog-6502@aaf4c084ef
|
2023-09-26 23:15:22 -07:00 |
|
Byron Lathi
|
915188e8f1
|
New test program that causes the error
|
2023-09-26 18:23:01 -07:00 |
|
Byron Lathi
|
c2dd5d616b
|
Gate rdy behind sdram_cs #28
|
2023-09-25 23:45:23 -07:00 |
|
Byron Lathi
|
4ee21f23b6
|
Up the sim time
|
2023-09-25 19:13:06 -07:00 |
|
Byron Lathi
|
95e05292cc
|
Fix clocks, define RTL_SIM
|
2023-09-24 23:58:32 -07:00 |
|
Byron Lathi
|
be68b4c9f9
|
Change sdrclk and sysclk to have aligned rising edges
|
2023-09-24 14:53:38 -07:00 |
|
Byron Lathi
|
3fcfa4d3ac
|
Add REPO_TOP env var
|
2023-09-24 10:35:17 -07:00 |
|
Byron Lathi
|
9bd031e35e
|
Add support for test programs
|
2023-09-24 10:29:32 -07:00 |
|