Alex Forencich
|
fa2385aedb
|
lss: Add I2C single register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 12:15:47 -07:00 |
|
Alex Forencich
|
44c811f82a
|
lss: Add I2C master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 10:41:16 -07:00 |
|
Alex Forencich
|
1e3e298d9e
|
Add cocotbext-i2c to tox.ini
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 10:18:03 -07:00 |
|
Alex Forencich
|
a86f858116
|
docs: Add readthedocs yaml file
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-18 16:23:30 -07:00 |
|
Alex Forencich
|
115bacae02
|
docs: Add sphinx infrastructure
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-18 16:12:49 -07:00 |
|
Alex Forencich
|
3624976f0e
|
hip: Add support for optional phase shifter clock to fractional MMCM module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-17 21:05:49 -07:00 |
|
Alex Forencich
|
d7e29a2b5c
|
hip: Add support for optional cascaded MMCM for offset clock
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-17 21:04:52 -07:00 |
|
Alex Forencich
|
b468d92e39
|
hip: Report error if fractional MMCM configuration does not work
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-17 21:00:12 -07:00 |
|
Alex Forencich
|
eacae099bf
|
hip: Add fractional MMCM wrapper for generating offset clocks for DDMTD
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-13 21:00:09 -07:00 |
|
Alex Forencich
|
ebeadee172
|
lss: Implement fractional baud rate generation for UART
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 23:49:39 -07:00 |
|
Alex Forencich
|
1c686391ab
|
lss: Refactor UART module to split out and share baud rate generation logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 23:09:19 -07:00 |
|
Alex Forencich
|
7df14e54e5
|
xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 18:33:57 -07:00 |
|
Alex Forencich
|
8d4ad59727
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 17:04:03 -07:00 |
|
Alex Forencich
|
15653923fd
|
xfcp: Add XFCP switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 15:30:59 -07:00 |
|
Alex Forencich
|
0ee729b744
|
xfcp: Add XFCP AXI module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:28:05 -07:00 |
|
Alex Forencich
|
70d77c8a95
|
xfcp: Add XFCP AXI lite module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:25:55 -07:00 |
|
Alex Forencich
|
ed9e8ffab3
|
eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 11:05:58 -08:00 |
|
Alex Forencich
|
6e4988f010
|
eth: Fix PFC/LFC tests for 10G MAC+PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 10:41:49 -08:00 |
|
Alex Forencich
|
cb04b84e18
|
example/VCU118: Add example design for VCU118
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 00:29:17 -08:00 |
|
Alex Forencich
|
024353c68a
|
lss: Add MDIO master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 23:48:57 -08:00 |
|
Alex Forencich
|
ed325acb1e
|
axis: Implement tstrb in pipeline FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:18:20 -08:00 |
|
Alex Forencich
|
e9ac4947ba
|
axis: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:17:05 -08:00 |
|
Alex Forencich
|
56215865da
|
axi: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:16:29 -08:00 |
|
Alex Forencich
|
c422297666
|
axis: Tie off unused sideband signals in COBS encoder
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-06 16:11:38 -08:00 |
|
Alex Forencich
|
194a686bda
|
xfcp: Add XFCP UART interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-04 22:05:11 -08:00 |
|
Alex Forencich
|
98ea651532
|
axis: Use unpacked arrays for unpacking interface signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:56 -08:00 |
|
Alex Forencich
|
56a3c9f1ba
|
axis: Add AXI stream arbitrated multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:40 -08:00 |
|
Alex Forencich
|
46e60d32f2
|
prim: Add arbiter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:49 -08:00 |
|
Alex Forencich
|
5966d05740
|
prim: Add priority encoder and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:32 -08:00 |
|
Alex Forencich
|
a790e270b8
|
axi: Replace reg with logic in AXI lite RAM
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:44:18 -08:00 |
|
Alex Forencich
|
df300b7dad
|
axis: Add AXI stream multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:28:02 -08:00 |
|
Alex Forencich
|
aa9900de94
|
axi: Add STRB parameters to testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 10:06:56 -08:00 |
|
Alex Forencich
|
ff2e3c1331
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:59:30 -08:00 |
|
Alex Forencich
|
ad3042e090
|
axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:58:30 -08:00 |
|
Alex Forencich
|
55c097f47d
|
axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:27:11 -08:00 |
|
Alex Forencich
|
0632b1982e
|
axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:26:03 -08:00 |
|
Alex Forencich
|
c478f187b1
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:09:29 -08:00 |
|
Alex Forencich
|
ae26b61200
|
axi: Add AXI register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:08:39 -08:00 |
|
Alex Forencich
|
1075896ecc
|
axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:02:50 -08:00 |
|
Alex Forencich
|
5e5bce9aa0
|
axi: Add SV interface for AXI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:51:25 -08:00 |
|
Alex Forencich
|
5f9f71e615
|
axi: Add SV interface for AXI lite
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:51:16 -08:00 |
|
Alex Forencich
|
f419b3167a
|
axis: Switch AXI stream interface license to MIT
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 20:50:40 -08:00 |
|
Alex Forencich
|
da3996cf5c
|
example/ADM_PCIE_9V3: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 14:16:18 -08:00 |
|
Alex Forencich
|
c6cbb57fe7
|
lss: Extract UART data width setting from interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 14:15:42 -08:00 |
|
Alex Forencich
|
07d75f231a
|
eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:35:09 -08:00 |
|
Alex Forencich
|
01f836a2f9
|
example/KR260: Remove drive strength settings from input pins
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:18:08 -08:00 |
|
Alex Forencich
|
cf44abae0d
|
axis: Use signal sync module for async FIFO output pause
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:13:10 -08:00 |
|
Alex Forencich
|
181691941f
|
eth: Use signal sync module for RGMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:12:50 -08:00 |
|
Alex Forencich
|
f8d5d6a45e
|
eth: Use signal sync module for GMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:12:10 -08:00 |
|
Alex Forencich
|
64c1cb1e39
|
eth: Use signal sync module for internal MAC pause handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 16:27:37 -08:00 |
|