Alex Forencich
|
cd52e44ae2
|
eth: Add timeout to AN implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-02 01:33:35 -07:00 |
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Alex Forencich
|
9c5cdb990b
|
eth: Rework AN timer implementation to use a separate prescaler
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-07-02 01:17:21 -07:00 |
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Alex Forencich
|
e6fe163e17
|
eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-30 00:33:21 -07:00 |
|
Alex Forencich
|
5f9e16d56c
|
eth: Add support for 1000BASE-X autonegotiation to 1000BASE-X MAC+PCS
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-30 00:32:05 -07:00 |
|
Alex Forencich
|
be7f5b5d27
|
eth: Add support for 1000BASE-X autonegotiation to 1000BASE-X PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-29 17:17:04 -07:00 |
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Alex Forencich
|
d2745a6a4a
|
eth: Remove extraneous default values
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-23 17:17:11 -07:00 |
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Alex Forencich
|
771e4de9eb
|
eth: Support ordered sets in AXI stream-BASE-R encode/decode logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-19 22:58:27 -07:00 |
|
Alex Forencich
|
67078fd39e
|
eth: Support ordered sets in AXI stream-XGMII encode/decode logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-19 21:05:59 -07:00 |
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Alex Forencich
|
6706b9b30b
|
eth: Test ordered sets via XGMII in XGMII-BASE-R encode/decode modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-19 20:40:07 -07:00 |
|
Alex Forencich
|
cb8ee730e6
|
ci: Update cocotbext-eth
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-19 20:38:55 -07:00 |
|
Alex Forencich
|
0220b73b8f
|
eth: Fix transcoding of signal ordered sets in XGMII-BASE-R encode module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-19 16:49:32 -07:00 |
|
Alex Forencich
|
62c544444b
|
eth: Support ordered sets in XGMII-BASE-R encode/decode logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-18 22:02:58 -07:00 |
|
Alex Forencich
|
3c2c86e35f
|
eth: Support ordered sets in 10GBASE-R simulation model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-18 21:59:43 -07:00 |
|
Alex Forencich
|
e39ac2fd9c
|
eth: Use shift registers for AN match counts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-18 12:40:11 -07:00 |
|
Alex Forencich
|
dd0b0c616c
|
eth: Fix AN match counts
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-17 23:48:13 -07:00 |
|
Alex Forencich
|
2e53313c41
|
eth: Suport AN config reg exchange in AXI stream-BASE-X encode/decode logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-17 16:48:20 -07:00 |
|
Alex Forencich
|
3a0c0057d4
|
eth: Suport AN config reg exchange in GMII-BASE-X encode/decode logic
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-17 16:34:44 -07:00 |
|
Alex Forencich
|
f4a986b4fd
|
eth: Support AN config register exchange in 1000BASE-X simulation model
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-17 16:34:26 -07:00 |
|
Alex Forencich
|
424f721ea3
|
eth: Fix assignment type
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-16 12:18:40 -07:00 |
|
Alex Forencich
|
debfcbaa18
|
eth: Minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-12 12:18:34 -07:00 |
|
Alex Forencich
|
16db68e161
|
eth: Add 1000BASE-X PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-12 11:35:44 -07:00 |
|
Alex Forencich
|
507143fbcf
|
eth: Add GMII-1000BASE-X encode/decode modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-12 10:20:15 -07:00 |
|
Alex Forencich
|
6e1e9c905f
|
ci: Update cocotbext-eth
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-11 17:28:25 -07:00 |
|
Alex Forencich
|
923beaf58d
|
eth: Update timestamp handling in testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-11 01:29:41 -07:00 |
|
Alex Forencich
|
8427a6c12b
|
eth: Fix timestamp point in taxi_axis_gmii_tx
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-10 23:16:18 -07:00 |
|
Alex Forencich
|
8d48453215
|
eth: Improve frame start/end timestamps in simulation models
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-09 23:13:54 -07:00 |
|
Alex Forencich
|
22d402ee50
|
eth: Simulation speed optimization
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-09 20:04:02 -07:00 |
|
Alex Forencich
|
2957a0ced9
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-08 21:43:09 -07:00 |
|
Alex Forencich
|
7f9e9980ce
|
eth: Update ZCU102 example design to use BASE-X core for 1G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-08 21:24:16 -07:00 |
|
Alex Forencich
|
da63de1c43
|
eth: Update ZCU106 example design to use BASE-X core for 1G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-08 21:23:44 -07:00 |
|
Alex Forencich
|
e42f11f1fb
|
eth: Update KCU105 example design to use BASE-X core for 1G
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-08 21:11:56 -07:00 |
|
Alex Forencich
|
148d0987f4
|
eth: Parameter cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-08 00:44:03 -07:00 |
|
Alex Forencich
|
8ec23b7d55
|
eth: Add UltraScale GT wrappers for 1000BASE-X MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-07 23:34:05 -07:00 |
|
Alex Forencich
|
d85d6a05b9
|
eth: Handle truncated premable in 1000BASE-X modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-04 21:42:40 -07:00 |
|
Alex Forencich
|
ee76d39fda
|
eth: Update BASE-X PFC test
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-04 19:06:06 -07:00 |
|
Alex Forencich
|
90bbb8a780
|
eth: Fix BASE-R model timestamping
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-06-04 17:39:19 -07:00 |
|
Alex Forencich
|
251921bfce
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-31 20:18:16 -07:00 |
|
Alex Forencich
|
531bef64b8
|
eth: Add 1000BASE-X MAC/PHY combination modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-31 20:03:21 -07:00 |
|
Alex Forencich
|
283eb45a5c
|
eth: Enable more test cases
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-31 14:21:39 -07:00 |
|
Alex Forencich
|
416aa4281d
|
eth: Remove extraneous parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-31 13:49:11 -07:00 |
|
Alex Forencich
|
ee111ad7a7
|
eth: Add AXI stream 1000BASE-X TX/RX modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-31 12:10:53 -07:00 |
|
Alex Forencich
|
82d07c40e2
|
eth: Add missing parameter connection in testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-31 12:03:46 -07:00 |
|
Alex Forencich
|
0111c7cdc6
|
eth: Clean up IFG handling in 10G/25G MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-28 23:22:57 -07:00 |
|
Alex Forencich
|
c0465679b2
|
eth: Clean up GT instance naming
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-27 14:51:17 -07:00 |
|
Alex Forencich
|
de90c91d37
|
eth: Gearbox is always used on 7-series
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-14 16:11:56 -07:00 |
|
Alex Forencich
|
3951a565b5
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-12 13:06:02 -07:00 |
|
Alex Forencich
|
39a53f0dd7
|
cndm: Update designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-12 12:09:48 -07:00 |
|
Alex Forencich
|
09c583c7be
|
cndm_proto: Update designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-12 01:47:00 -07:00 |
|
Alex Forencich
|
3541463c91
|
eth: Update example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-12 01:46:11 -07:00 |
|
Alex Forencich
|
0745952e14
|
eth: Fix testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2026-05-12 00:36:59 -07:00 |
|