Alex Forencich
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cb04b84e18
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example/VCU118: Add example design for VCU118
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-07 00:29:17 -08:00 |
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Alex Forencich
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024353c68a
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lss: Add MDIO master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-06 23:48:57 -08:00 |
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Alex Forencich
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ed325acb1e
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axis: Implement tstrb in pipeline FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-06 16:18:20 -08:00 |
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Alex Forencich
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e9ac4947ba
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axis: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-06 16:17:05 -08:00 |
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Alex Forencich
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56215865da
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axi: Normalize unpacked dimension
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-06 16:16:29 -08:00 |
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Alex Forencich
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c422297666
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axis: Tie off unused sideband signals in COBS encoder
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-06 16:11:38 -08:00 |
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Alex Forencich
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194a686bda
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xfcp: Add XFCP UART interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-04 22:05:11 -08:00 |
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Alex Forencich
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98ea651532
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axis: Use unpacked arrays for unpacking interface signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-28 23:24:56 -08:00 |
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Alex Forencich
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56a3c9f1ba
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axis: Add AXI stream arbitrated multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-28 23:24:40 -08:00 |
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Alex Forencich
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46e60d32f2
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prim: Add arbiter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-28 21:04:49 -08:00 |
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Alex Forencich
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5966d05740
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prim: Add priority encoder and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-28 21:04:32 -08:00 |
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Alex Forencich
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a790e270b8
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axi: Replace reg with logic in AXI lite RAM
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 13:44:18 -08:00 |
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Alex Forencich
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df300b7dad
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axis: Add AXI stream multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 13:28:02 -08:00 |
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Alex Forencich
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aa9900de94
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axi: Add STRB parameters to testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 10:06:56 -08:00 |
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Alex Forencich
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ff2e3c1331
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:59:30 -08:00 |
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Alex Forencich
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ad3042e090
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axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:58:30 -08:00 |
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Alex Forencich
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55c097f47d
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axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:27:11 -08:00 |
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Alex Forencich
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0632b1982e
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axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:26:03 -08:00 |
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Alex Forencich
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c478f187b1
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 21:09:29 -08:00 |
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Alex Forencich
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ae26b61200
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axi: Add AXI register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 21:08:39 -08:00 |
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Alex Forencich
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1075896ecc
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axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 21:02:50 -08:00 |
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Alex Forencich
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5e5bce9aa0
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axi: Add SV interface for AXI
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 20:51:25 -08:00 |
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Alex Forencich
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5f9f71e615
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axi: Add SV interface for AXI lite
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 20:51:16 -08:00 |
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Alex Forencich
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f419b3167a
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axis: Switch AXI stream interface license to MIT
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 20:50:40 -08:00 |
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Alex Forencich
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da3996cf5c
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example/ADM_PCIE_9V3: Example design cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 14:16:18 -08:00 |
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Alex Forencich
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c6cbb57fe7
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lss: Extract UART data width setting from interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 14:15:42 -08:00 |
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Alex Forencich
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07d75f231a
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eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:35:09 -08:00 |
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Alex Forencich
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01f836a2f9
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example/KR260: Remove drive strength settings from input pins
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:18:08 -08:00 |
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Alex Forencich
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cf44abae0d
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axis: Use signal sync module for async FIFO output pause
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:13:10 -08:00 |
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Alex Forencich
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181691941f
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eth: Use signal sync module for RGMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:12:50 -08:00 |
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Alex Forencich
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f8d5d6a45e
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eth: Use signal sync module for GMII MAC speed detection
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 17:12:10 -08:00 |
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Alex Forencich
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64c1cb1e39
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eth: Use signal sync module for internal MAC pause handling
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 16:27:37 -08:00 |
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Alex Forencich
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84fb93b5c3
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example: Add signal sync timing constraints to example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 16:04:32 -08:00 |
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Alex Forencich
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8785c1517b
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example/fb2CG: Add example design for fb2CG@KU15P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 15:49:21 -08:00 |
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Alex Forencich
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5a8ac23922
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io: Add LED shift register driver module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 15:44:57 -08:00 |
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Alex Forencich
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6e90f4f0a0
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syn: Add timing constraints for signal synchronizer
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 15:39:00 -08:00 |
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Alex Forencich
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eae85cb8c7
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syn: Clean up timing constraints for reset sync
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 15:38:39 -08:00 |
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Alex Forencich
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d0c7d7735a
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example/Nexus_K3P_Q: Reorganize MAC instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 12:20:01 -08:00 |
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Alex Forencich
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abb0ca1bcc
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example/ADM_PCIE_9V3: Reorganize MAC instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 12:01:20 -08:00 |
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Alex Forencich
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b18b643eed
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example/Alveo: Add example design for Xilinx Alveo series
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 11:34:26 -08:00 |
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Alex Forencich
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4cdc4be47e
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example/ADM_PCIE_9V3: Testbench cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-24 21:42:23 -08:00 |
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Alex Forencich
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ffe667b047
|
example/Nexus_K3P_Q: Add example design for Cisco Nexus K3P-Q
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-24 21:39:26 -08:00 |
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Alex Forencich
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8ffbd43e08
|
example/Nexus_K3P_S: Add example design for Cisco Nexus K35-S/K3P-S
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-24 21:04:42 -08:00 |
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Alex Forencich
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916355ca8a
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eth: Add TX/RX polarity control to MAC+PHY+GT wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-24 17:17:23 -08:00 |
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Alex Forencich
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7047cb5c4f
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eth: Tie off transceiver control signals during simulation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-24 16:28:59 -08:00 |
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Alex Forencich
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34266fe25d
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example/ZCU111: Add example design for ZCU111
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-23 17:32:21 -08:00 |
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Alex Forencich
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27033384d9
|
example: Update GPIO constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-23 16:24:15 -08:00 |
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Alex Forencich
|
2fa899373e
|
Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-23 14:13:42 -08:00 |
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Alex Forencich
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f424eb3f98
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example/ADM-PCIE-9V3: Clean up makefiles
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-23 14:13:17 -08:00 |
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Alex Forencich
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aedf4d5c4c
|
example/ZCU106: Fix width
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-23 14:12:57 -08:00 |
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