Alex Forencich
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ad3042e090
|
axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:58:30 -08:00 |
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Alex Forencich
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55c097f47d
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axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:27:11 -08:00 |
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Alex Forencich
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0632b1982e
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axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:26:03 -08:00 |
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Alex Forencich
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ae26b61200
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axi: Add AXI register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 21:08:39 -08:00 |
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Alex Forencich
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1075896ecc
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axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 21:02:50 -08:00 |
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Alex Forencich
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c6cbb57fe7
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lss: Extract UART data width setting from interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 14:15:42 -08:00 |
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Alex Forencich
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07d75f231a
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eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:35:09 -08:00 |
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Alex Forencich
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7613cae4f0
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eth: Use 2D array for PFC config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-22 22:08:43 -08:00 |
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Alex Forencich
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6a294cef2c
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Use string type for string parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-21 19:14:28 -08:00 |
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Alex Forencich
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6154506c0a
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axis: Use reset synchronizer module in AXI stream async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-20 12:44:23 -08:00 |
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Alex Forencich
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c6ca108392
|
eth: Clean up testbench clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:45:19 -08:00 |
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Alex Forencich
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94dba88560
|
eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:42 -08:00 |
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Alex Forencich
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255b26d2f2
|
eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:22 -08:00 |
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Alex Forencich
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baa5f72a6c
|
eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:16:54 -08:00 |
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Alex Forencich
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ffaf05f2d1
|
eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:05:59 -08:00 |
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Alex Forencich
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c0583aaff5
|
eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:37:12 -08:00 |
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Alex Forencich
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175230eeaf
|
eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:46:31 -08:00 |
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Alex Forencich
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d01a90298c
|
eth: Use correct clock for TX completions in MAC + FIFO testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:59:18 -08:00 |
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Alex Forencich
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5c8037093b
|
eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:06:41 -08:00 |
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Alex Forencich
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fc1e0efad7
|
ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:07:46 -08:00 |
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Alex Forencich
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ad0d44616b
|
ptp: Add PTP TD leaf clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 20:18:17 -08:00 |
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Alex Forencich
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2eaa2f64a2
|
ptp: Add PTP TD PHC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:50:16 -08:00 |
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Alex Forencich
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38a150b87a
|
ptp: Add PTP period output module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:06:46 -08:00 |
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Alex Forencich
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2abe774f8a
|
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:48:54 -08:00 |
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Alex Forencich
|
90650aee69
|
eth: Add 10G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:47:54 -08:00 |
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Alex Forencich
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f356fad6fe
|
ptp: Add PTP clock CDC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 12:49:42 -08:00 |
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Alex Forencich
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17b4c37a1e
|
ptp: Add PTP clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 10:52:27 -08:00 |
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Alex Forencich
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8a67eaa220
|
eth: Clean up testbench parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:35:18 -08:00 |
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Alex Forencich
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04b73e7ddf
|
eth: Add 1G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:12:57 -08:00 |
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Alex Forencich
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8f8572bdee
|
eth: Add taxi_axis_if to MAC file list files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 15:54:15 -08:00 |
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Alex Forencich
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2616e3f3e3
|
eth: Add 10G Ethernet combined MAC+PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:40:50 -08:00 |
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Alex Forencich
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0ddb89b18f
|
eth: Add 10G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:26:03 -08:00 |
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Alex Forencich
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fa73f9c1d5
|
eth: Add 1G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:25:48 -08:00 |
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Alex Forencich
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8d3d703656
|
eth: Add MAC control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 19:59:11 -08:00 |
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Alex Forencich
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96e348ac84
|
eth: Invert TX completion output control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 23:24:28 -08:00 |
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Alex Forencich
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1c381ce22e
|
eth: Enable tuser signals
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 22:23:03 -08:00 |
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Alex Forencich
|
72dabc5a9a
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:23 -08:00 |
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Alex Forencich
|
2af4e7af3e
|
eth: Add AXI stream 64-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:15 -08:00 |
|
Alex Forencich
|
a375eb342d
|
eth: Add AXI stream 32-bit XGMII Ethernet frame transmitter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:03:06 -08:00 |
|
Alex Forencich
|
c914adf9f1
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 18:02:48 -08:00 |
|
Alex Forencich
|
e3f047d735
|
eth: Add AXI stream 64-bit BASE-R Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:27:27 -08:00 |
|
Alex Forencich
|
f0f2a25943
|
eth: Add AXI stream 64-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:54 -08:00 |
|
Alex Forencich
|
8046a46680
|
eth: Add AXI stream 32-bit XGMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:25:06 -08:00 |
|
Alex Forencich
|
3f501aaac9
|
eth: Add AXI stream GMII Ethernet frame receiver module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-07 16:12:58 -08:00 |
|
Alex Forencich
|
d52aa2f97e
|
axis: Add AXI stream combination async FIFO/adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-06 00:52:04 -08:00 |
|
Alex Forencich
|
69e5ae8545
|
axis: Add AXI stream async FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-06 00:46:39 -08:00 |
|
Alex Forencich
|
584f2a6542
|
eth: Add MAC pause control modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 21:11:14 -08:00 |
|
Alex Forencich
|
f479a85155
|
lfsr: Add LFSR descrambler module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:29:12 -08:00 |
|
Alex Forencich
|
e6ea90be36
|
lfsr: Add LFSR scrambler module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:28:57 -08:00 |
|
Alex Forencich
|
aeedc3bf7d
|
lfsr: Add LFSR PRBS checker module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-05 15:28:31 -08:00 |
|