Alex Forencich
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77313e1ed0
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eth: Add example design for Alibaba AS02MC04
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-05 14:35:33 -08:00 |
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Alex Forencich
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b0dd91aa8d
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dma: Add UltraScale PCIe DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-04 17:18:26 -08:00 |
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Alex Forencich
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14d988d1f2
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dma: Add AXI DMA interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-04 12:41:07 -08:00 |
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Alex Forencich
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851919f16f
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dma: Add AXI stream sink DMA client module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-03 21:30:55 -08:00 |
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Alex Forencich
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5b0c83fc57
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dma: Add AXI streaming DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-03 17:14:24 -08:00 |
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Alex Forencich
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9442bb7fbb
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dma: Add AXI central DMA module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-03 11:42:04 -08:00 |
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Alex Forencich
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999602cf11
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-03 09:24:04 -08:00 |
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Alex Forencich
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4e099af53a
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math: Add MT19937 Mersenne Twister PRNG module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-10-15 22:14:21 -07:00 |
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Alex Forencich
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a74a49cffb
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xfcp: Add XFCP module for APB
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-30 21:01:17 -07:00 |
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Alex Forencich
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88018ac9e8
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axi: Add AXI lite to APB adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-30 16:14:17 -07:00 |
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Alex Forencich
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952232ad66
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apb: Add APB dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-30 15:25:21 -07:00 |
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Alex Forencich
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f25e41de18
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apb: Add APB RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-30 15:24:56 -07:00 |
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Alex Forencich
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81a918d223
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apb: Add SV interface for APB
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-06 16:50:38 -07:00 |
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Alex Forencich
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20f14ace97
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-09-06 07:06:50 -07:00 |
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Alex Forencich
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cdfb1566f5
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-31 21:38:06 -07:00 |
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Alex Forencich
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e87e16c299
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axi: Add AXI FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 22:17:53 -07:00 |
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Alex Forencich
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0080125120
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axi: Add AXI to AXI lite adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 21:11:20 -07:00 |
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Alex Forencich
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94a821192c
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axi: Add AXI width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 21:10:08 -07:00 |
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Alex Forencich
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e43d6acbbd
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axi: Add AXI lite to AXI adapter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 13:40:43 -07:00 |
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Alex Forencich
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c22e659259
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axi: Add AXI lite width converter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-30 13:02:27 -07:00 |
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Alex Forencich
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4dd84efd6c
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-29 18:00:22 -07:00 |
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Alex Forencich
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65cb6124c4
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-02 21:20:34 -07:00 |
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Alex Forencich
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d4089096ae
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example: Add example design for HTG-9200
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-02 21:19:58 -07:00 |
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Alex Forencich
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4620370035
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lss: Add I2C slave AXI lite master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-02 00:44:14 -07:00 |
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Alex Forencich
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37825a02f4
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lss: Add I2C slave module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-02 00:22:11 -07:00 |
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Alex Forencich
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933899887a
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axis: Add AXI stream switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-07-31 11:47:49 -07:00 |
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Alex Forencich
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bd0b0cd75a
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Update documentation URL
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-07-30 19:12:45 -07:00 |
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Alex Forencich
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d10e3cf5c0
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axis: Add AXI stream demultiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-07-30 19:10:48 -07:00 |
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Alex Forencich
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b266aa2949
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axis: Add AXI stream concatenator module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-07-30 18:57:11 -07:00 |
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Alex Forencich
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7bfc62d0d2
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example: Add example design for BittWare XUP-P3R/XUSP3S
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-02 00:08:20 -07:00 |
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Alex Forencich
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b0bdf8ee17
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-26 00:13:12 -07:00 |
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Alex Forencich
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8ecb68ae01
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-25 00:04:54 -07:00 |
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Alex Forencich
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2fd346269f
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xfcp: Add XFCP I2C master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 15:56:39 -07:00 |
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Alex Forencich
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fa2385aedb
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lss: Add I2C single register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 12:15:47 -07:00 |
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Alex Forencich
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44c811f82a
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lss: Add I2C master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 10:41:16 -07:00 |
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Alex Forencich
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8d4ad59727
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-10 17:04:03 -07:00 |
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Alex Forencich
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cb04b84e18
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example/VCU118: Add example design for VCU118
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-07 00:29:17 -08:00 |
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Alex Forencich
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024353c68a
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lss: Add MDIO master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-06 23:48:57 -08:00 |
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Alex Forencich
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df300b7dad
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axis: Add AXI stream multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 13:28:02 -08:00 |
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Alex Forencich
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ff2e3c1331
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:59:30 -08:00 |
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Alex Forencich
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ad3042e090
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axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:58:30 -08:00 |
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Alex Forencich
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55c097f47d
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axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:27:11 -08:00 |
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Alex Forencich
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0632b1982e
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axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-27 00:26:03 -08:00 |
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Alex Forencich
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c478f187b1
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-26 21:09:29 -08:00 |
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Alex Forencich
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8785c1517b
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example/fb2CG: Add example design for fb2CG@KU15P
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 15:49:21 -08:00 |
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Alex Forencich
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b18b643eed
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example/Alveo: Add example design for Xilinx Alveo series
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-25 11:34:26 -08:00 |
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Alex Forencich
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ffe667b047
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example/Nexus_K3P_Q: Add example design for Cisco Nexus K3P-Q
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-24 21:39:26 -08:00 |
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Alex Forencich
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8ffbd43e08
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example/Nexus_K3P_S: Add example design for Cisco Nexus K35-S/K3P-S
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-24 21:04:42 -08:00 |
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Alex Forencich
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34266fe25d
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example/ZCU111: Add example design for ZCU111
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-23 17:32:21 -08:00 |
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Alex Forencich
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2fa899373e
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Update readme
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-23 14:13:42 -08:00 |
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