Alex Forencich
|
8dc33f3a44
|
eth: Use shared counter for fractional part of pause quanta
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-26 20:02:35 -07:00 |
|
Alex Forencich
|
01c0c6cdc6
|
stats: Add strings collector
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 22:40:53 -07:00 |
|
Alex Forencich
|
e6cf1f5850
|
eth: Add statistics strings to Ethernet MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 21:35:50 -07:00 |
|
Alex Forencich
|
031d092513
|
stats: Add string support to statistics collector
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 17:08:52 -07:00 |
|
Alex Forencich
|
e3fcf54466
|
stats: Add gate input to statistics collector
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-16 11:54:16 -07:00 |
|
Alex Forencich
|
1f1c15ba8d
|
stats: Add max increment rate test
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-10 21:59:27 -07:00 |
|
Alex Forencich
|
93d9c8c9f6
|
eth: Add MAC statistics module to 10G MAC+PCS
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-09 12:18:42 -07:00 |
|
Alex Forencich
|
e90340db6e
|
eth: Add MAC statistics module to 1G MACs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-08 20:22:53 -07:00 |
|
Alex Forencich
|
bb90cd5a08
|
eth: Add MAC statistics module to 10G MAC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-08 20:18:43 -07:00 |
|
Alex Forencich
|
f920e56348
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_rx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:37:29 -07:00 |
|
Alex Forencich
|
c69eb63a69
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:29:50 -07:00 |
|
Alex Forencich
|
a53d18b9d3
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_32
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 23:28:59 -07:00 |
|
Alex Forencich
|
f8890e4d80
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_tx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:03:26 -07:00 |
|
Alex Forencich
|
4fd3028f77
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_64
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:01:57 -07:00 |
|
Alex Forencich
|
6d31116596
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_32
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 22:00:34 -07:00 |
|
Alex Forencich
|
07e781e186
|
eth: Improve oversize frame tests
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 17:21:36 -07:00 |
|
Alex Forencich
|
1b28dc4b9a
|
eth: Check stats outputs in AXI stream GMII RX module testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 13:32:03 -07:00 |
|
Alex Forencich
|
b073fc8efb
|
eth: Check stats outputs in AXI stream GMII TX module testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-07 13:25:53 -07:00 |
|
Alex Forencich
|
0ef0bb3409
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_rx
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-06 00:17:31 -07:00 |
|
Alex Forencich
|
5582eddfa8
|
eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_tx
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-04-05 22:15:39 -07:00 |
|
Alex Forencich
|
5b16933210
|
eth: Test more lengths to shift alignment
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-26 23:13:13 -07:00 |
|
Alex Forencich
|
bec324dc03
|
eth: Fix bugs in 10G MAC RX related to short IFGs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-26 23:03:57 -07:00 |
|
Alex Forencich
|
4f830c8a12
|
axi: Remove extraneous interface declarations
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-25 00:03:42 -07:00 |
|
Alex Forencich
|
d2b0fa4693
|
stats: Add statistics counter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-25 00:02:58 -07:00 |
|
Alex Forencich
|
fd3e23ef6e
|
stats: Add statistics collector module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-24 23:22:04 -07:00 |
|
Alex Forencich
|
2fd346269f
|
xfcp: Add XFCP I2C master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 15:56:39 -07:00 |
|
Alex Forencich
|
b8021192e3
|
lss: Clean up I2C testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 14:52:26 -07:00 |
|
Alex Forencich
|
79e0bf6976
|
lss: Remove redundant tristate control outputs on I2C modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 12:41:39 -07:00 |
|
Alex Forencich
|
fa2385aedb
|
lss: Add I2C single register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 12:15:47 -07:00 |
|
Alex Forencich
|
44c811f82a
|
lss: Add I2C master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-19 10:41:16 -07:00 |
|
Alex Forencich
|
ebeadee172
|
lss: Implement fractional baud rate generation for UART
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 23:49:39 -07:00 |
|
Alex Forencich
|
7df14e54e5
|
xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-11 18:33:57 -07:00 |
|
Alex Forencich
|
15653923fd
|
xfcp: Add XFCP switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 15:30:59 -07:00 |
|
Alex Forencich
|
0ee729b744
|
xfcp: Add XFCP AXI module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:28:05 -07:00 |
|
Alex Forencich
|
70d77c8a95
|
xfcp: Add XFCP AXI lite module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:25:55 -07:00 |
|
Alex Forencich
|
ed9e8ffab3
|
eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 11:05:58 -08:00 |
|
Alex Forencich
|
6e4988f010
|
eth: Fix PFC/LFC tests for 10G MAC+PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 10:41:49 -08:00 |
|
Alex Forencich
|
194a686bda
|
xfcp: Add XFCP UART interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-04 22:05:11 -08:00 |
|
Alex Forencich
|
56a3c9f1ba
|
axis: Add AXI stream arbitrated multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:40 -08:00 |
|
Alex Forencich
|
46e60d32f2
|
prim: Add arbiter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:49 -08:00 |
|
Alex Forencich
|
5966d05740
|
prim: Add priority encoder and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:32 -08:00 |
|
Alex Forencich
|
df300b7dad
|
axis: Add AXI stream multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:28:02 -08:00 |
|
Alex Forencich
|
aa9900de94
|
axi: Add STRB parameters to testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 10:06:56 -08:00 |
|
Alex Forencich
|
ad3042e090
|
axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:58:30 -08:00 |
|
Alex Forencich
|
55c097f47d
|
axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:27:11 -08:00 |
|
Alex Forencich
|
0632b1982e
|
axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:26:03 -08:00 |
|
Alex Forencich
|
ae26b61200
|
axi: Add AXI register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:08:39 -08:00 |
|
Alex Forencich
|
1075896ecc
|
axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:02:50 -08:00 |
|
Alex Forencich
|
c6cbb57fe7
|
lss: Extract UART data width setting from interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 14:15:42 -08:00 |
|
Alex Forencich
|
07d75f231a
|
eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:35:09 -08:00 |
|