Alex Forencich
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2fd346269f
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xfcp: Add XFCP I2C master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 15:56:39 -07:00 |
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Alex Forencich
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b8021192e3
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lss: Clean up I2C testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 14:52:26 -07:00 |
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Alex Forencich
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79e0bf6976
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lss: Remove redundant tristate control outputs on I2C modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 12:41:39 -07:00 |
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Alex Forencich
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fa2385aedb
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lss: Add I2C single register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 12:15:47 -07:00 |
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Alex Forencich
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44c811f82a
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lss: Add I2C master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-19 10:41:16 -07:00 |
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Alex Forencich
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ebeadee172
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lss: Implement fractional baud rate generation for UART
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-11 23:49:39 -07:00 |
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Alex Forencich
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7df14e54e5
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xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-11 18:33:57 -07:00 |
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Alex Forencich
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15653923fd
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xfcp: Add XFCP switch module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-10 15:30:59 -07:00 |
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Alex Forencich
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0ee729b744
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xfcp: Add XFCP AXI module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-03-10 13:28:05 -07:00 |
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Alex Forencich
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70d77c8a95
|
xfcp: Add XFCP AXI lite module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-10 13:25:55 -07:00 |
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Alex Forencich
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ed9e8ffab3
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eth: Use unpacked arrays for multidimensional ports
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 11:05:58 -08:00 |
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Alex Forencich
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6e4988f010
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eth: Fix PFC/LFC tests for 10G MAC+PHY
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-07 10:41:49 -08:00 |
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Alex Forencich
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194a686bda
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xfcp: Add XFCP UART interface module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-03-04 22:05:11 -08:00 |
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Alex Forencich
|
56a3c9f1ba
|
axis: Add AXI stream arbitrated multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 23:24:40 -08:00 |
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Alex Forencich
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46e60d32f2
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prim: Add arbiter module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:49 -08:00 |
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Alex Forencich
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5966d05740
|
prim: Add priority encoder and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-28 21:04:32 -08:00 |
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Alex Forencich
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df300b7dad
|
axis: Add AXI stream multiplexer module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 13:28:02 -08:00 |
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Alex Forencich
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aa9900de94
|
axi: Add STRB parameters to testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 10:06:56 -08:00 |
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Alex Forencich
|
ad3042e090
|
axi: Add AXI lite dual-port RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:58:30 -08:00 |
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Alex Forencich
|
55c097f47d
|
axi: Add AXI RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:27:11 -08:00 |
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Alex Forencich
|
0632b1982e
|
axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-27 00:26:03 -08:00 |
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Alex Forencich
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ae26b61200
|
axi: Add AXI register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:08:39 -08:00 |
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Alex Forencich
|
1075896ecc
|
axi: Add AXI lite register module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 21:02:50 -08:00 |
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Alex Forencich
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c6cbb57fe7
|
lss: Extract UART data width setting from interface
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-26 14:15:42 -08:00 |
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Alex Forencich
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07d75f231a
|
eth: Fix testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-25 17:35:09 -08:00 |
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Alex Forencich
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7613cae4f0
|
eth: Use 2D array for PFC config
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-22 22:08:43 -08:00 |
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Alex Forencich
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6a294cef2c
|
Use string type for string parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-21 19:14:28 -08:00 |
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Alex Forencich
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6154506c0a
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axis: Use reset synchronizer module in AXI stream async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-20 12:44:23 -08:00 |
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Alex Forencich
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c6ca108392
|
eth: Clean up testbench clocking
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:45:19 -08:00 |
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Alex Forencich
|
94dba88560
|
eth: Add RGMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:42 -08:00 |
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Alex Forencich
|
255b26d2f2
|
eth: Add GMII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:17:22 -08:00 |
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Alex Forencich
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baa5f72a6c
|
eth: Add MII Ethernet MAC with FIFOs module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:16:54 -08:00 |
|
Alex Forencich
|
ffaf05f2d1
|
eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 22:05:59 -08:00 |
|
Alex Forencich
|
c0583aaff5
|
eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 21:37:12 -08:00 |
|
Alex Forencich
|
175230eeaf
|
eth: Add MII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 20:46:31 -08:00 |
|
Alex Forencich
|
d01a90298c
|
eth: Use correct clock for TX completions in MAC + FIFO testbenches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:59:18 -08:00 |
|
Alex Forencich
|
5c8037093b
|
eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-16 18:06:41 -08:00 |
|
Alex Forencich
|
fc1e0efad7
|
ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 22:07:46 -08:00 |
|
Alex Forencich
|
ad0d44616b
|
ptp: Add PTP TD leaf clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 20:18:17 -08:00 |
|
Alex Forencich
|
2eaa2f64a2
|
ptp: Add PTP TD PHC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:50:16 -08:00 |
|
Alex Forencich
|
38a150b87a
|
ptp: Add PTP period output module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 17:06:46 -08:00 |
|
Alex Forencich
|
2abe774f8a
|
eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:48:54 -08:00 |
|
Alex Forencich
|
90650aee69
|
eth: Add 10G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 13:47:54 -08:00 |
|
Alex Forencich
|
f356fad6fe
|
ptp: Add PTP clock CDC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 12:49:42 -08:00 |
|
Alex Forencich
|
17b4c37a1e
|
ptp: Add PTP clock module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-13 10:52:27 -08:00 |
|
Alex Forencich
|
8a67eaa220
|
eth: Clean up testbench parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:35:18 -08:00 |
|
Alex Forencich
|
04b73e7ddf
|
eth: Add 1G Ethernet MAC module with FIFOs and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 22:12:57 -08:00 |
|
Alex Forencich
|
8f8572bdee
|
eth: Add taxi_axis_if to MAC file list files
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-11 15:54:15 -08:00 |
|
Alex Forencich
|
2616e3f3e3
|
eth: Add 10G Ethernet combined MAC+PHY module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:40:50 -08:00 |
|
Alex Forencich
|
0ddb89b18f
|
eth: Add 10G Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2025-02-08 21:26:03 -08:00 |
|