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Author SHA1 Message Date
Byron Lathi
af60d32679 Remove RAM memory section 
Replace RAM section with SDRAM.

Really this makes no difference than before we added SDRAM except the
name is different. In hardware, the SDRAM acts the same way and is
located in the same space as the RAM was previously.
 2022-03-21 14:06:12 -05:00
Byron Lathi
74210f57f7 Remove fpga RAM 
This removes the ram from inside the FPGA. All RAM is now located in the
external SDRAM instead.

The ROM is still in the FPGA to allow easier programming.
 2022-03-21 14:01:16 -05:00
Byron Lathi
c97f2d807a Merge branch 'board-io' into 'master' 
Add board-io, replace sevenseg in sw

See merge request bslathi19/super6502!8
 2022-03-18 01:27:55 +00:00
Byron Lathi
5c32fe808e Add board-io, replace sevenseg in sw 2022-03-18 01:27:55 +00:00
Byron Lathi
63b942e29a Merge branch 'sdram' into 'master' 
Add SDRAM controller (controller)

See merge request bslathi19/super6502!7
 2022-03-17 22:57:16 +00:00
Byron Lathi
42a718408d Move SDRAM and state machine into its own file 
Cleans up the top level module a bit
 2022-03-17 17:49:20 -05:00
Byron Lathi
7cb3183f85 Add sdram to address decode test 2022-03-17 17:12:43 -05:00
Byron Lathi
7619c7c54f new testing program 2022-03-17 15:05:37 -05:00
Byron Lathi
bbba99d099 Move data data segment to SDRAM 2022-03-17 15:05:25 -05:00
Byron Lathi
ee97c4cbaa Add platform generation to build stage 2022-03-17 14:25:26 -05:00
Byron Lathi
2d49fe22a7 ignore .sopcinfo 
This will be generated automatically when built.
 2022-03-17 13:53:07 -05:00
Byron Lathi
2a1f8df54e Create SDRAM memory region 2022-03-17 13:37:34 -05:00
Byron Lathi
15e3ae9688 Add SDRAM controller (controller) 
Turns out there are some issues with holding the chip select for the
SDRAM controller high for too long, so there is a simple 2-state fsm
which ensures that the chip select is only held for 1 clock cycle for
writes and for as long as it takes to read the data from sdram for
reads.
 2022-03-17 13:31:56 -05:00
Byron Lathi
aa337c61d5 Create sdram platform 2022-03-15 23:45:57 -05:00
Byron Lathi
c0d7766bc6 Merge branch 'conio' into 'master' 
Add conio

See merge request bslathi19/super6502!6
 2022-03-15 15:03:19 +00:00
Byron Lathi
15b91dcc20 Add conio 
Also removes print statements from the interrupt handler (except for the
button interrupt)
 2022-03-14 22:20:15 -05:00
Byron Lathi
340f43103a Fix bug where A was overwritten in _uart_txb_block 
If you wanted to transmit a value and then check what it was, you can do
that now.
 2022-03-14 22:19:19 -05:00
Byron Lathi
a627d38778 Ignore all output files 2022-03-14 16:58:44 -05:00
Byron Lathi
ac3f5a0fca Merge branch 'uart-irq' into 'master' 
Add UART Receive logic

See merge request bslathi19/super6502!5
 2022-03-14 21:56:27 +00:00
Byron Lathi
8e161664bb Add uart_rxb 
Once you receive a uart interrupt you can call this function to get the
received character.
 2022-03-14 16:48:24 -05:00
Byron Lathi
59d2d4f601 Add receive logic to UART 
The UART has a receive buffer which will fill up when it receives bytes.
Once the buffer is full, it raises the RX flag until the value is read
by the cpu.
 2022-03-14 16:41:59 -05:00
Byron Lathi
ed18b381f3 Change "clkdiv" to "tx_clkdiv" 2022-03-14 15:22:18 -05:00
Byron Lathi
264263b0d9 Change "state" to "tx_state" etc. 2022-03-14 15:10:59 -05:00
Byron Lathi
b2344d986e Add UART interrupts 
Currently an interrupt is triggered any time there is any activity on
the UART_RXD line, but later it will only trigger once there is data
ready to be read.
 2022-03-14 14:57:45 -05:00
Byron Lathi
0316d047e3 Merge branch 'irqs' into 'master' 
Add interrupt status register

See merge request bslathi19/super6502!4
 2022-03-14 19:04:30 +00:00
Byron Lathi
f5dbe46060 Add irq_set_status 
irq_set_status can be used to clear the irq status bit so that the
interrupt will stop occuring.
 2022-03-14 13:34:33 -05:00
Byron Lathi
a5474b5ae5 Implement interrupt status register 
Upon an interrupt, you can read from the interrupt status register to
see what caused the interrupt.
 2022-03-14 13:30:01 -05:00
Byron Lathi
e012eb7d4d Exclude vectors from list of test objects 
We do not need this, since there are no interrupts during tests.
 2022-03-14 13:27:29 -05:00
Byron Lathi
e70fffb472 Add irq status register 
Upon receiving an interrupt, the corresponding bit in the interrupt
status register will be set and an IRQ will be raised for the CPU. The
cpu can then respond to the interrupt and clear the interrupt by writing
back to the interrupt status register.
 2022-03-14 13:16:09 -05:00
Byron Lathi
26070313f4 Ignore greybox_tmp 2022-03-14 13:15:20 -05:00
Byron Lathi
fe45331e7a Add interrupt handlers and redo vector locations 
Most of these are taken from
https://cc65.github.io/doc/customizing.html, but modified to suit this
setup.
 2022-03-14 11:54:43 -05:00
Byron Lathi
ff78fd0179 Connect Button 1 to cpu_irqb 
A maskable interrupt can be generated by pressing button 1, the reset
button remains button 0.
 2022-03-14 11:53:45 -05:00
Byron Lathi
5560b06c9f Merge branch 'uart' into 'master' 
Add UART TX Module

See merge request bslathi19/super6502!3
 2022-03-14 16:02:04 +00:00
Byron Lathi
4fb73f8e97 Update cs_testbench.sv 
Add uart_cs and fix error messages
 2022-03-14 10:56:15 -05:00
Byron Lathi
a671fda51c Add sample puts function 
"Hello, world!" :)
 2022-03-14 10:46:36 -05:00
Byron Lathi
cfcf94a875 Integrate uart controller into top level module 
Adds new chip select for the UART, and a new entry in the data_out mux
for the UART.
 2022-03-14 10:45:45 -05:00
Byron Lathi
da4d5f0fe7 Add uart tests 2022-03-14 00:47:26 -05:00
Byron Lathi
0b5ccf48b8 Add basic UART driver 
This didn't have a chance to get tested so I hope it works.

There is not fancy stuff here, just write to the register and wait till
it is done.
 2022-03-14 00:24:08 -05:00
Byron Lathi
b48438f6b2 Add write and puts tasks to the uart testbench 
The write task will transmit a single byte, the puts task will transmit
a string of length n. These do not do any verification, you still have
to look at the output.
 2022-03-14 00:04:04 -05:00
Byron Lathi
f8da9206d9 Refactor uart.sv to better allow cpu control 
Added new signal tx_flag, which indicates whether the transmitter is
ready for new data.

Added status register, which when read will return the tx_flag bit, as
well as others that can be implemented.

Added new state IDLE, which resets the TX flag and allows new data to be
written.

Added code to allow for different baud rates, though it is still fixed
currently.
 2022-03-14 00:00:55 -05:00
Byron Lathi
e063e9f6a3 Add basic UART device 
So far the device only transmits the ASCII set on repeat, but will
become fully featured later.
 2022-03-13 19:42:41 -05:00
Byron Lathi
5834f179d2 Ignore more modelsim files 
Ignore all bak files and msim_transcript
 2022-03-13 19:39:14 -05:00
Byron Lathi
36ff20e587 Update Makefile 
Add source as comment in assembly listings.
 2022-03-12 22:40:48 -06:00
Byron Lathi
45af469029 Merge branch 'hex_driver' into 'master' 
Add full seven segment display driver

See merge request bslathi19/super6502!2
 2022-03-13 04:23:11 +00:00
Byron Lathi
d229052ed6 Add hex tests 2022-03-12 22:17:41 -06:00
Byron Lathi
a6bcadab6e Fix bugs in sevenseg.s 
Fixed bug where we forgot to restore x in _hex_set_8 if the idx check
fails. We did remember to restore it if the check passed.

Fixed bug where _hex_set_24 did not return 0.
 2022-03-12 22:10:37 -06:00
Byron Lathi
1a9290b97b Implement hex_set_24 2022-03-12 21:55:17 -06:00
Byron Lathi
226a2972cc Implement hex_set_16 2022-03-12 21:49:47 -06:00
Byron Lathi
c8a7cc4153 Implement enable byte in sw 2022-03-12 21:46:08 -06:00
Byron Lathi
c7e8cc3798 Implement enable byte in hw 2022-03-12 21:45:30 -06:00